Low Power SAR-ADC Using 180nm CMOS Technology

Authors

  • Shraddha Naik B.E. Student, Department of Electronics and Telecommunications Engineering, Don Bosco Institute of Technology, Mumbai, India
  • Bhoomi Patel B.E. Student, Department of Electronics and Telecommunications Engineering, Don Bosco Institute of Technology, Mumbai, India
  • Chaitali Poojary B.E. Student, Department of Electronics and Telecommunications Engineering, Don Bosco Institute of Technology, Mumbai, India
  • Sudhakar Mande Professor, Department of Electronics and Telecommunications Engineering, Don Bosco Institute of Technology, Mumbai, India

Keywords:

CMOS, Ngspice, OTA, SAR ADC, SCL

Abstract

This paper involves designing of Successive Approximation Register (SAR) Analog-to-Digital converter (ADC) and its implementation in 180nm SCL technology using Ngspice. The paper presents a low power 14-bit, 10Mbps SAR ADC. Low-power design technique has been utilized to achieve the low power consumption that is less than 300mW. ADC is designed in 180nm CMOS technology with a 3.3V power supply and a 10Mbps sampling rate. To achieve low power consumption Charge Scaling DAC, two stage OTA for Sample and Hold and low power D-Flip Flop is used in SAR design.

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Published

30-09-2020

Issue

Section

Articles

How to Cite

[1]
S. Naik, B. Patel, C. Poojary, and S. Mande, “Low Power SAR-ADC Using 180nm CMOS Technology”, IJRESM, vol. 3, no. 9, pp. 150–154, Sep. 2020, Accessed: May 27, 2024. [Online]. Available: https://journal.ijresm.com/index.php/ijresm/article/view/316