Design and Analysis of Nanoscale Two Stage OTA


  • Shubham Shende Student, Department of Electronics and Communication Engineering, National Institute of Technology Rourkela, Rourkela, India
  • Sudhakar Mande Professor, Department of Electronics and Telecommunication Engineering, Don Bosco Institute of Technology, Mumbai, India


CMOS, OTA, optimization, advancements


This electronic document describes the implementation of a CMOS two-stage OTA in the Nanoscale technology. There are various approaches to design the amplifier circuit viz. a traditional approach of designing OTA using pole-zero, gain bandwidth, slew rate, loading effect information and calculating the aspect ratios of MOSFET. Another approach is the method of approximation concerning the design theory. Most of the electronic devices consume large area and power which is undesirable. Hence it is important to reduce the size and power consumption. Designing analogue circuits not only requires a rethink of the typical architecture of OPAMPs and OTAs regarding the number of stacked transistors to avail maximum swing but also it requires the attention on necessary inversion level of the MOS transistors to support lower supply voltages and optimum voltages and optimum power-performance level.


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How to Cite

S. Shende and S. Mande, “Design and Analysis of Nanoscale Two Stage OTA”, IJRESM, vol. 5, no. 5, pp. 58–61, May 2022.




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