Energy Efficient Power Gated True Single Phase Clocked Flip Flop with Redundant Precharge Free Operation

Abstract

The project represents the analysis of a novel energy gated true single phased clock (TSPC) flip flop. Optimizing the power is a major aspect in many applications. The concept of the project attributes to present D flip-flop circuit using header power gating technique which is significantly used for low power operation. The task of the analysis is to verify the energy loss of the data flip flop in the suspected functional design. This proposed design is implemented in Tanner EDA tool. The evaluation and simulation output shows a huge decrease in energy consumption for this proposed cell with power gating.