Design of D Flip Flop as a Frequency Divider by Using Folded CMOS Current Mode Logic

Authors

  • Sahana Udupa Student, Department of Electronics and Communication Engineering, East West Institute of Technology, Bangalore, India
  • M. Anand Associate Professor, Department of Electronics and Communication Engineering, East West Institute of Technology, Bangalore, India

Keywords:

FMCML, MCML DFF, DIV2, Frequency divider, Scaler architecture

Abstract

This project presents a fixed frequency divider built on FMCML flops. Since common-mode issues might develop when employing only one type of FMCML flip-flop, the idea is based on switching FMCML flops using CMOS input differential duo. Our method avoids intermediate stages by making use of Frequency divide by 16 by adopting FCMCML D Latch having complementary transistors. An adapting approach is discussed here such that it makes use of Scaler architecture with 4 NMOS having an enable pin so that it attains minimal power dissipation and reduction in overall delay.

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Published

13-07-2022

Issue

Vol. 5 No. 7 (2022)

Section

Articles

License

Copyright (c) 2022 Sahana Udupa, M. Anand

Creative Commons License

This work is licensed under a Creative Commons Attribution 4.0 International License.

How to Cite

[1]
S. Udupa and M. Anand, “Design of D Flip Flop as a Frequency Divider by Using Folded CMOS Current Mode Logic”, IJRESM, vol. 5, no. 7, pp. 38–41, Jul. 2022, Accessed: Apr. 25, 2024. [Online]. Available: https://journal.ijresm.com/index.php/ijresm/article/view/2262