High Security and Low Power Nano AES Security Algorithm for Image Cryptography

Abstract

Advanced Encryption Standard (AES) is a type of data encryption. It is one of the most widely used encryption method and implemented in both software and hardware. On a field programmable gate array, this cryptographic technique is implemented (FPGA). The suggested design consists of five operating blocks and employs an 8-bit data channel. For the storage of plain text, keys, and intermediate data, we employ two types of registers: Key-Register and State-Register. Shift-Rows are insert-ed within the State-Register Mix-Columns to save space. They are constructed with four internal registers that take and return 8-bits. Optimized for sharing for the key expansion and encryption phases, sub-bytes are assigned. To reduce power consumption, we implement the clock gating technique in the design. This paper presents an Image Cryptography based 128-bit AES design. The Design will be implemented on FPGA XC3S 200 TQ-144 kit using Verilog HDL as programming language and its design is simulated by Modelsim 6.4 c. The synthesis process is done through Xilinx tool.