High Performance on Truncated MAC Units of Digital Filtering in the Residue Number

Abstract

The Residue Number System is used to create a finite impulse response filter for this project (RNS). The benefits of using the selected moduli set are the same as using the shift and add method. The developed filter architecture is compared to a traditional version of a reprogrammable Residue Number System FIR filter. The filters and the RTL diagram for the Field programmable gate array execution were both produced using the Vivado Design Suite 2018.1 platform (FPGA). The area (A), delay (T), and power (P) of the filters are all examined (P). The trial discoveries uncover that the proposed method has better implementation as far as deferral, region postpone item, region, and energy power item. The proposed methodology is also functionally proven on the Artix-7 Field Programmable Gate Array to evaluate digital signal processing builder.