Implementation and Analysis of Wallace Tree Multiplier Using Kogge Stone Adder and Sklansky Adder

Abstract

Multiplier is the most dominant block in DSP systems, Embedded and VLSI applications. So, it is necessary to design a multiplier which provides high performance. Power consumption, area occupied and delay are the key features which determines the performance of a multiplier. When the process of multiplication is initiated, it gives rise to partial products and it also necessitate to sum the partial products to carry out this process half adder and full adder is used, which takes more time and area for calibration. This paper mainly focuses on implementation of 16X16 bits multiplier using Wallace tree approach with 15-4 compressor. The partial products are compressed using 5-3 compressor along with half adder and full adders. In the enclosure stage parallel prefix adders such as Kogge Stone adder and Sklansky adder are utilized for the partial product addition. The obtained results of both multipliers are compared, and analyzed that Sklansky adder is better in terms of area (Number of LUT’s).