Low Power Programmable PRPG with the Test Compression Capabilities

Authors

  • Parthiban Ravi UG Student, Department of Electronics and Communication Engineering, Bannari Amman Institute of Technology, Erode, India
  • M. Mano Sakthi UG Student, Department of Electronics and Communication Engineering, Bannari Amman Institute of Technology, Erode, India
  • S. Abin Satheesan Assistant Professor, Department of Electronics and Communication Engineering, Bannari Amman Institute of Technology, Erode, India
  • R. Saravana Kumar Assistant Professor, Department of Electronics and Communication Engineering, Bannari Amman Institute of Technology, Erode, India

Keywords:

Low Power, Pseudorandom test pattern generators (PRPGs), Test Patterns, Test data volume compression

Abstract

This paper presents a low power pseudo random sample generator with desired preselected toggling activity. The proposed structure has a linear comments shift sign in or a ring generator (linear finite nation machine) which drives section shifter and it produces binary sequences with low switching price. This could have the first-class test insurance possible in comparison with the great-to-date conventional BIST-primarily based PRPGs. In this proposed gadget we introduce with negligible effect on check application time and deterministically manual the take a look at pattern generator toward test sequences with the intention to enhance the ratio of fault-coverage-to sample-count number. The above proposed hybrid system successfully combines test compression with Logic BIST to supply high high-quality tests. The gadget is applied the usage of HDL and the simulation and synthesis reports are shown.

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Published

23-08-2020

How to Cite

[1]
P. Ravi, M. M. Sakthi, S. A. Satheesan, and R. S. Kumar, “Low Power Programmable PRPG with the Test Compression Capabilities”, IJRESM, vol. 3, no. 8, pp. 384–387, Aug. 2020.

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Articles