Structure Design Engineering for Optimal Analog Performance of Nanowire Junctionless MOSFET

Abstract

Analog performance of silicon nanowire junction less MOSFET (SNW-JL-MOSFET) in the sub-20 nm regime is investigated using a device simulator, namely ATLAS. It is observed that optimal selection of structure parameters of SNW-JL-MOSFET attains higher drain current, peak trans conductance and output conductance. This proposed architecture also provides better analog frequency parameters and switching speed of the device and is very useful for circuit design. The gate dielectric material optimization of the structure is attained through via broad device simulation. In this manuscript, a study is carried for the SCEs like SS, DIBL and significantly for analog parameters like trans conductance and output conductance.