Design of Low Power Comparator in 90nm Technology for ADC Application

Authors

  • K. S. Bhumika Student, Department of Electronics and Communication Engineering, Sapthagiri College of Engineering, Bengaluru, India
  • Mallika R. Babu Student, Department of Electronics and Communication Engineering, Sapthagiri College of Engineering, Bengaluru, India
  • K. C. Inchara Student, Department of Electronics and Communication Engineering, Sapthagiri College of Engineering, Bengaluru, India
  • Sameena A. Nadaf Student, Department of Electronics and Communication Engineering, Sapthagiri College of Engineering, Bengaluru, India
  • P. Prathibha Assistant Professor, Department of Electronics and Communication Engineering, Sapthagiri College of Engineering, Bengaluru, India

Keywords:

Power dissipation, ADC, Dynamic comparator, Technology, Pre-Amplifier comparator

Abstract

Comparators are the most underrated and under-utilized monolithic linear component. In today’s generation power dissipation is the most criteria in affecting the circuit we need to reduce the power dissipation. Choosing the best comparator for application is necessary. Here dynamic comparator has been designed and obtained a power dissipation of 78.14uW which is less than the power dissipation of pre-amplifier-based comparator. Design of low power comparator in 90nm technology for ADC application is done using cadence tool.

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Published

25-07-2021

Issue

Vol. 4 No. 7 (2021)

Section

Articles

License

Copyright (c) 2021 K. S. Bhumika, Mallika R. Babu, K. C. Inchara, Sameena A. Nadaf, P. Prathibha

Creative Commons License

This work is licensed under a Creative Commons Attribution 4.0 International License.

How to Cite

[1]
K. S. Bhumika, M. R. Babu, K. C. Inchara, S. A. Nadaf, and P. Prathibha, “Design of Low Power Comparator in 90nm Technology for ADC Application”, IJRESM, vol. 4, no. 7, pp. 293–297, Jul. 2021, Accessed: Dec. 21, 2024. [Online]. Available: https://journal.ijresm.com/index.php/ijresm/article/view/1075